篇題：Energy-Saving Logic Gates Utilizing Coupling Phenomenon Between MIS(p) Tunneling Diodes
文章出處：IEEE Transactions on Electron Devices, Vol. 68, No.12, December, PP. 6558-6562 (DOI: 10.1109/TED. 2021.3122414)
作者：Jen Hao Chen, Kung Chu Chen and Jenn Gwo Hwu*
任職單位及部門：國立臺灣大學電子工程學研究所
In this work, based on coupling mechanism between Al/SiO2/Si(p) metal-insulator-semiconductor (MIS) tunneling diodes (TD), a multi-level open-circuit voltage sensor was developed. With selected input voltage signals applied at several outer MIS TDs and open-circuit voltage read at inner MIS TD serving as output signal, multiple levels of Vout-Vin curves can be achieved. The mechanism behind this phenomenon is related to charge coupling between two adjacent MIS TDs. According to this result, a novel concept of logic gates accommodating multiple inputs and with ultra-low power consumption was further proposed. Finally, a 2D TCAD simulation was implemented to confirm our speculation and experimental result. This notion is believed to overcome the difficulties about sophisticated logic function encountered in conventional CMOS circuit and be extremely conducive to logic computation on electronics chip in the future.
文章摘要：
本研究利用 Al/SiO2/Si(p) 金屬-絕緣體-半導體 (MIS) 穿隧二極體 (TD) 之間的耦合機制，開發了一種多位準開路電壓感測器。將選定的輸入電壓信號施加在幾個外部 MIS TD 處，並在內部 MIS TD 處讀取開路電壓作為輸出信號，可以實現多位準之 Vout-Vin 曲線。本現象與兩個相鄰的 MIS TD 之間的電荷耦合機制有關，根據實驗觀察，進一步提出了一種可容納多個輸入且具有超低功耗的邏輯閘的新穎構想。同時經由 2D TCAD 模擬來確認所提的推測和驗證實驗結果。相信這個概念可以克服傳統CMOS電路中複雜的邏輯功能所遇到的困難，並且有機會應用於未來晶片上的邏輯計算。