篇題：A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process
文章出處：IEEE Electron Device, vol. 68, no. 12, pp.6644 - 6647 , 31 Dec. 2021 DOI: 10.1109/TED.2021.3120707
作者：Bing-Yue Tsui , Senior Member, IEEE, Te-Kai Tsai, Yen-Ting Lu, Jian-Hao Lin, Chia-Lung Hung , and Yu-Xin Wen
任職單位及部門：國立陽明交通大學 電子研究所
The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO2 and the impact of the defect layer on devices. The deeplevel transient spectroscopy(DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N+/P-junction exhibits stronger temperature dependence than that of the P+/N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensiveSiC N+/P-junction by 42 times at 150 ◦C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V.
文章摘要：
預非晶化離子注入 (PAI) 可以大幅提高 SiC 的氧化速率，近年氬離子(Ar)的 PAI 技術已用於形成 SiC 的局部氧化 (LOCOSiC) 結構，用於 SiC積體電路 (IC) 中的元件隔離。這篇論文介紹了預非晶化的SiC經過熱氧化後，SiO2 下面的缺陷層的研究，以及缺陷層對元件的影響。深能階暫態光譜(DLTS)分析表明缺陷層由大量C空位和Si空位組成。長邊長型的 N+/P 接面的漏電流表現出比 P+/N 接面更強的溫度依賴性。該結果證實 C 空位是 n 型 SiC 中的有效載子生命期殺手，但在 p 型 SiC 中則不然。儘管與傳統化學氣相沉積 (CVD) 場氧化層 (FOX)的接面相比，這些缺陷使長邊長型 SiC N+/P 接面在 150°C 下的漏電流增加了 42 倍，但漏電流仍然遠低於IC的關閉電流。缺陷層電阻高，很難讓SiC表面進入反型狀態，使得金氧半場效應電晶體的臨界電壓高於±24 V，證明LOCOSiC隔離結構有極佳的隔離能力。