篇題：A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process
文章出處：IEEE Electron Device, vol. 68, no. 12, pp.6644 - 6647 , 31 Dec. 2021 DOI: 10.1109/TED.2021.3120707
作者：Bing-Yue Tsui , Senior Member, IEEE, Te-Kai Tsai, Yen-Ting Lu, Jian-Hao Lin, Chia-Lung Hung , and Yu-Xin Wen
任職單位及部門：國立陽明交通大學 電子研究所
The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO2 and the impact of the defect layer on devices. The deeplevel transient spectroscopy(DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N+/P-junction exhibits stronger temperature dependence than that of the P+/N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensiveSiC N+/P-junction by 42 times at 150 ◦C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V.